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CA3450
January 1999 File Number 1732.5
220MHz, Video Line Driver, High Speed Operational Amplifier
The CA3450 is a large signal video line driver and high speed operational amplifier capable of driving 50 transmission lines and flash A/Ds. The uncompensated unity gain crossing occurs at 230MHz without load. It can operate at dual or single supplies of 7.25V or 14.5V, respectively. The CA3450 can be compensated with a single capacitor network. It has output drive capability of 75mA SINK or SOURCE. The CA3450 is capable of driving Flash A/Ds in video or high speed instrumentation (accurate) applications with bandwidth up to 10MHz. Offset voltage nulling terminals are also available.
Features
* High Open Loop Gain at Video Frequencies - AOL . . . . . . . . . . . . . . . . . . . . . . . . . . >40dB at f = 5MHz * Power Bandwidth of 10MHz . . . . . . . ACL = 5; VO = 3.5V * Slew Rate at Full Load . . . . . . . . . . . . . 330V/s (AV 10) * fT = 220MHz; CC = 0pF With a Load of 50 ||20pF|| 1M (Scope Input) * VOUT = 4.1V Into 75 * Offset Null Terminals
Applications
* Video Line Driver * High Frequency Unity Gain Buffer * Pulse Amplifier * High Speed Comparator
Pinout
CA3450 (PDIP) TOP VIEW
OFFSET NULL 1 NC 2 - INPUT 3 V- 4 V- 5 VO 6 V+ 7 V+ 8
16 OFFSET NULL 15 NC 14 + INPUT 13 V12 V11 COMP 10 NC 9 COMP
* High Frequency Oscillator and Video Amplifiers * Driver for A/Ds in Video Applications . . . . . . . .10MHz BW
Part Number Information
PART NUMBER CA3450E TEMP. RANGE (oC) -40 to 85 PACKAGE 16 Ld PDIP PKG. NO. E16.3
1
CAUTION: These devices are sensitive to electrostatic discharge; follow proper IC Handling Procedures. 1-888-INTERSIL or 321-724-7143 | Copyright (c) Intersil Corporation 1999
CA3450 Block Diagram
7 V+ 8 V+
BIAS CIRCUIT +IN 14 3 -IN INPUT CURRENT COMPENSATED DIFFERENTIAL AMPLIFIER DC LEVEL SHIFT STAGE OUTPUT POWER DRIVER AND OUTPUT POWER STAGE + X180 X0.50 X18 6 OUTPUT
-
1
16
9
11
4
5 V-
12
13
OFFSET NULL
PHASE COMP
Schematic Diagram
FREQUENCY COMPENSATION 11 D1 Q5 Q2 Q1 Q3 Q4 Q6 Q7 D2 C1 Q8 Q10 Q11 C2 Q12 Q17 VD3 VQ18 Q19 Q9 V+ 8 V+ 7
Q14 C3 Q16 Q15
D4 R5 2K R4 8.5K C4 D5 D6 R8 30 R6 2K C5 D10 Q35 C6
R7 6 6 OUTPUT 9 FREQUENCY COMPENSATION Q38 D9
V+
3 INVERTING INPUT
Q20 Q21 Q22 R2 140
Q23
14 NONINVERTING INPUT
Q26 R1 100K Q24 R9 780 R10 3.2K Q25 R11 3k D7 R12 250 Q28 C7 Q27
R3
Q29
Q30
Q31
Q32
Q33
Q34
Q36
Q37
R13 860
R14 860 1
R15 130
R16 860 16
R17 500
R18 200 4, 5, 12, 13
R19 100
R20 170
R21 270
R22 250
V-
2
CA3450
Absolute Maximum Ratings
Supply Voltage (Between V+ and V- Terminals) . . . . . . . . . . . 14.5V Differential Input Voltage . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .5V Output Current . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 100mA Operating Conditions Temperature Range . . . . . . . . . . . . . . . . . . . . . . . . . . -40oC to 85oC
Thermal Information
Thermal Resistance (Typical, Note 1) JA (oC/W) PDIP Package . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 60 Maximum Junction Temperature (Plastic Package) . . . . . . . .150oC Maximum Storage Temperature Range . . . . . . . . . . -65oC to 150oC Maximum Lead Temperature (Soldering 10s) . . . . . . . . . . . . 300oC
CAUTION: Stresses above those listed in "Absolute Maximum Ratings" may cause permanent damage to the device. This is a stress only rating and operation of the device at these or any other conditions above those indicated in the operational sections of this specification is not implied.
NOTE: 1. JA is measured with the component mounted on an evaluation PC board in free air.
Electrical Specifications
PARAMETER DC Input Offset Voltage
CC = 5pF, VSUPPLY = 6V, Unless Otherwise Specified SYMBOL TEST CONDITIONS TEMP. (oC) MIN TYP MAX UNITS
|VIO|
25 Full
60 55 55 50 3.5 3.0 -
8 10 100 50 70 65 60 3.7 30 -
20 35 400 200 40 50
mV mV nA nA dB dB dB dB V V mA mA
Input Bias current Input Offset Current Open Loop DC Gain
|IIB| |IIO| AOL VOUT = 2.5V, RL = 50 V = 1V VICR = 3.5V
25 25 25 Full
Power Supply Rejection Ratio Common Mode Rejection Ratio Common Mode Input Range
PSRR CMRR VICR
25 25 25 Full
Supply Current
I+
25 Full
DYNAMIC -3dB Bandwidth AV = 1 (See Figure 2) CC = 5pF Bandwidth (Unity Gain Crossing) AV = Open Loop CC = 0 (See Figure 1) Bandwidth (Unity Gain Crossing) AV = 10, CC = 0pF RFEEDBACK = 450 RPIN 3 - G = 50 (See Figure 2) No Load RL = 1M||20pF RL = 50||20pF No Load RL = 20pF||1M RL = 50||20pF No Load 50 1M||20pF 50||1M||20pF Transient Response, Overshoot (See Figure 3) OS AV = 1, CC = 5pF RL = 50||20pF No Load AV 10, CC = 0pF, RL = 50||20pF Settling Time (See Figure 5) (2V Step, RL = 50||20pF) tS AV = -1, CC = 5pF, 0.1%, 10 Bits AV = 1, CC = 5pF, 0.1%, 10 Bits AV = 10, CC = 0pF, 0.1%, 10 Bits AV = 10, CC = 0pF, 1.0%, 7 Bits 25 25 25 25 25 25 25 25 25 25 25 25 25 25 25 25 25 210 180 180 200 175 180 170 200 190 185 230 200 220 210 190 195 188 30 20 10 35 50 35 25 MHz MHz MHz MHz MHz MHz MHz MHz MHz MHz % % % ns ns ns ns
3
CA3450
Electrical Specifications
PARAMETER Slew Rate (See Figures 2, 4) CC = 5pF, VSUPPLY = 6V, Unless Otherwise Specified (Continued) SYMBOL SR TEST CONDITIONS AV = 1, CC = 5pF AV 10, CC = 0pF No Load RL = 50||20pF No Load RL = 50||20pF Full Power Bandwidth (FPBW = SR/ VP-P) FPBW AV = 5, CC = 5pF VOUT = 3.5V AV 10, CC = 0pF VOUT = 2.0V Input Noise Voltage Differential Gain Differential Phase Output Current Output Voltage Swing eN DG DP IOUT VOM+ VOM Input Capacitance Input Resistance Output Resistance CI RI ROUT See Figure 14, AV = 1, 30MHz f = 1MHz f = 1kHz See Figure 8 See Figure 8 Into +4V or -4V RL = 75 No Load RL = 50||20pF No Load RL = 50||20pF TEMP. (oC) 25 25 25 25 25 25 25 25 25 25 25 25 25 25 25 25 25 MIN 370 300 29 24 60 3.9 -3.9 TYP 220 160 440 330 10 7.2 35 26 12 0.2 0.2 75 4.1 -4.1 2.2 1 4 MAX UNITS V/s V/s V/s V/s MHz MHz MHz MHz nV/Hz % Degrees mA V V pF M
Test Circuits and Waveforms
0.1F + 10 (NOTE 2) +6V 4.7F (TANT.)
-
7 GEN 50 14 50 + 8 11 CC 9 CC CA3450 1 12 4 5 16 13 OFFSET NULL 10 (NOTE 2) -6V 4.7F (TANT.) 6 50 3 20pF 1M 0.001F SCOPE INPUT
-
0.1F
+
All 0.1F and 0.001F supply decoupling capacitors are multilayer ceramic chip types.
10 MULTILAYER 0.1F CERAMIC CHIP
51K
820pF SILVER MICA OR EQUIVALENT
NOTE: 2. A 10, 1/4W supply decoupling resistor is shown in all application circuits of this device. The resistor serves two purposes. First it provides a means of decoupling the IC directly at its terminal without introducing additional supply resonance due to parallel connected capacitors. Second, it also provides protection for the device in event of a sustained short circuit applied directly to the output terminals. FIGURE 1. OPEN LOOP GAIN vs FREQUENCY TEST CIRCUIT
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CA3450 Test Circuits and Waveforms
GEN 50 9 11 14 + 8 7 50 CA3450 15 3 6 0.1F
(Continued)
0pF (AV = 10) 5pF (AV = 1) 10 + +6V 4.7F (TANT.)
-
5 2 4 10
12 13 CABLE LENGTH 1M 10
CABLE LENGTH 1M
450 FOR AV = 10 3 50 6
0.1F
+
-6V 4.7F (TANT.)
TEKTRONIX 2465 OSCILLOSCOPE 50 50
FIGURE 2. UNITY GAIN AND X10 NON-INVERTING AMPLIFIER/AND SLEW RATE TEST CIRCUIT
Transient Response Waveforms
FIGURE 3. TRANSIENT RESPONSE WAVEFORM
FIGURE 4. SLEW RATE WAVEFORM
5
CA3450 Test Circuits and Waveforms
54 2-10pF 10 CC 11 9 INPUT 174 14 511 3 7 8 0.01 F +6V
(Continued)
11 10 9 8 7 BITS 6 5
2V STEP
CA3450 + 12 4 5 11 ALL RESISTORS ARE 1% 10 -6V 82.5 2 2-HP-5082-2835 DIODES 6 50 SIMULATED TWO TRANSMISSION LINE
4 3 2 1 15 20 25 30 35 40 45 50 SETTLING TIME TO 1/2LSB (ns)
MULTILAYER CERAMIC CHIP 0.1F 82.5 MEASUREMENT POINT
FIGURE 6. ACCURACY IN BITS AS A FUNCTION OF SETTLING TIME
10
15 1
0.5k
10k
0.5k 16
4 V-
FIGURE 5. CIRCUIT USED TO MEASURE SETTLING TIME
FIGURE 7. NULLING CIRCUIT FOR THE CA3450
5pF 10 MODULATED STAIRCASE INPUT SIGNAL 14 75 CA3450 15 3 11 9 + 8 7 75 6 1VP-P 75 220 13 10 4 TEKTRONIX VM700A NTSC TEST SET 0.1F +6V +
- 4.7F
SHIELDED CABLE
5 2
12
10 -6V 0.1F 4.7F 220
FIGURE 8. CONFIGURATION USED TO MEASURE DIFFERENTIAL GAIN AND PHASE
6
CA3450 Test Circuits and Waveforms
(Continued)
+8V 10 0.001F
7 75, 1VP-P VIDEO INPUT 75 5pF 9 3 14 + 11 10 CA3450 6 390 0.001F 13 5 16 21 FLASH A/D INPUT 8
4
12
10
750
110
-4V
0.1F 0V TO -10V OFFSET SOURCE, RS <10
FIGURE 9. TYPICAL HIGH BANDWIDTH X5 AMPLIFIER FOR DRIVING THE CA3318 FLASH A/D
Typical Performance Curves
60 55 50 45 40 35 30 25 20 15 10 5 0 -5 1 10 CLOSED LOOP GAIN (dB) 10 AV = 1 0 CC = 7pF -10 CC = 5pF CC = 5pF RL = 50, || 20pF CC = 0pF, TA = 25oC VS = 6V -85 -100 -115 -130 -145 -160 -175 -190 -205 -220 -235 -250 -265
35o MARGIN
PHASE ANGLE (DEGREES)
OPEN LOOP GAIN (dB)
0 45
CC = 7pF
PHASE SHIFT AOL 100
90 135 180
1000
1
FREQUENCY (MHz)
10 FREQUENCY (MHz)
100
300
FIGURE 10. BODE PLOT FOR THE CA3450
FIGURE 11. CLOSED LOOP GAIN AND PHASE vs FREQUENCY
7
PHASE (DEGREES)
CA3450 Typical Performance Curves
30 AV = 10 CLOSED LOOP GAIN (dB) 20 GAIN 10 PHASE 45 0 90 135 -10 1 10 FREQUENCY (MHz) 100 180 300 0
(Continued)
EQUIVALENT INPUT NOISE VOLTAGE (nV/Hz)
100
PHASE (DEGREES)
10
1 101
102
103 104 FREQUENCY (MHz)
105
106
FIGURE 12. CLOSED LOOP GAIN AND PHASE vs FREQUENCY
FIGURE 13. EQUIVALENT INPUT NOISE vs FREQUENCY
100 OUTPUT VOLTAGE SWING (VP-P) 90 OUTPUT RESISTANCE () 80 70 60 50 40 30 20 10 0 1 10 FREQUENCY (MHz) 100 200
10.0 9.0 8.0 7.0 6.0 5.0 4.0 3.0 2.0 1.0 0.0 1 10 FREQUENCY (MHz) 100 300 RL = 50 || 20pF AV = 10, CC = 0pF RL = 660 || 20pF RL = 75 || 20pF
FIGURE 14. OUTPUT RESISTANCE vs FREQUENCY
FIGURE 15. OUTPUT VOLTAGE vs FREQUENCY
Metallization Mask Layout
0 66 60 50 40 30 20 10 0 106 (2.692) 66 (1.676) 10 20 30 40 50 60 70 80 90 100 106
Dimensions in parenthesis are in millimeters and are derived from the basic inch dimensions as indicated. Grid graduations are in mils (10-3 inch). The photographs and dimensions of each CMOS chip represent a chip when it is part of the wafer. When the wafer is cut into chips, the angle of cleavage may vary with respect to the chip face for different chips. The actual dimensions of the isolated chip, therefore, may differ slightly from the nominal dimensions shown. The user should consider a tolerance of -3mils to +6mils applicable to the nominal dimensions shown.
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